DSP56857 datasheet(374/662 Pages) FREESCALE

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Counting Modes Definitions

5685X Digital Signal Controller User Manual, Rev. 4

13-8

Freescale Semiconductor

counters are operating in a ripple mode, where higher order counters will transition a

clock later than a purely synchronous design.

13.7.10 Pulse Output Mode

The Counter will output a pulse stream of pulses with the same frequency of the selected clock

source (can not be IPBus clock divided by one) if the counter is setup for:

•

Count mode (mode = 001)

•

The OFLAG Output mode is set to 111 (Gated Clock Output)

•

The Count Once bit is set

The number of output pulses is equal to the compare value minus the initial value. This mode is

useful for driving step motor systems.

Note:

Primary count source must be set to one of the counter outputs for gated clock output

mode.

13.7.11 Fixed Frequency PWM Mode

The Counter output yields a Pulse Width Modulated (PWM) signal with a frequency equal to the

count clock frequency divided by 65,536. It has a pulse width duty cycle equal to the compare

value divided by 65,536 if the counter is setup for:

•

Count mode (mode = 001)

•

Count through roll-over (Count Length = 0)

•

Continuous count (Count Once = 0)

•

OFLAG Output mode is 110 (set on compare, cleared on counter rollover)

This mode of operation is often used to drive PWM amplifiers used to power motors and

inverters.

13.7.12 Variable Frequency PWM Mode

If the counter is setup for:

•

Count mode (Mode = 001)

•

Count till compare (Count Length = 1)

•

Continuous count (Count Once = 0)

•

OFLAG Output mode is 100 (toggle OFLAG and alternate compare registers)

the counter output yields a Pulse Width Modulated (PWM) signal whose frequency and pulse

width is determined by the values programmed into the TMR_CMP1 and TMR_CMP2 registers,

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