DSP56857 datasheet(455/662 Pages) FREESCALE

455 / 662 page

Servicing the Host Interface

Host Interface Eight (HI8), Rev. 4

Freescale Semiconductor

16-29

Figure 16-17. HI8 Transmit Byte Low Register (TXL)

See Programmer’s Sheet on Appendix page B - 146

* Depends on HLEND setting

16.10.5 Host Side Registers After Reset

Table 16-13 shows the result of the three kinds of reset on bits in each of the HI8 registers seen

by the Host Processor. The hardware reset is caused by asserting the RESET pin. Execute the

RESET instruction to set the software reset. Execute the STOP instruction to set the Stop reset.

Base + $7/$6*

Read

Write

TXL

Reset

00000000

Table 16-13.

Host Side Registers After Reset

Name

Data

Reset Type

Hardware

Reset

Software

Reset

Stop Reset

ICR

All Bits

—

CVR

HV[6:0]

$00

—

ISR

HREQ

1 if TREQ is set, 0 if TREQ is cleared

DMA

—

HF[3:2]

—

TRDY

TXDE

RXDF

IVR

IV[7:0]

$0F

—

RXH:RXL

Empty

TXH:TXL

Empty

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