DSP56857 datasheet(462/662 Pages) FREESCALE

462 / 662 page

Servicing the Host Interface

5685X Digital Signal Controller User Manual, Rev. 4

16-36

Freescale Semiconductor

The only potential system problem with the uncertainty of reading any status bits by the

Host is HF3 and HF2 as an encoded pair. For example, if the DSC changes HF3 and HF2

from 00 to 11, there is a very small probability the Host could read the bits during the

transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has

significance, the Host would potentially read the wrong combination.

Solutions:

• Read the bits twice and check for consensus.

• Assert HCS access for HCS + 1.5 Clock cycles so the status bit transitions are

stabilized.

4. Overwriting the Host Vector

The Host programmer should change the Host Vector register only when the Host

Command (HC) bit is clear. This guarantees the DSC interrupt control logic receives a

stable vector.

5. Cancelling a pending Host Command Exception

The Host Processor may elect to clear the HC bit to cancel the Host Command exception request

at any time before it is recognized by the DSC. The DSC may execute the Host exception after

the HC bit is cleared:

•

Because the Host does not know exactly when the exception is recognized

•

Because of synchronization

•

Because of exception processing pipelining. As a result, the HV must not be changed at

the same time the HC bit is cleared. In this way, if the exception was taken, the vector is

known.

16.10.10.2 DSC Programmer Considerations

Reading HF1 and HF0 as an encoded pair:

•DMA

•HF1

•HF0

•HCP

•HTDE

•HRDF

DSP56857 데이터시트(PDF) 462 Page - Freescale Semiconductor, Inc