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DSP56857 데이터시트(PDF) 546 Page - Freescale Semiconductor, Inc |
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DSP56857 데이터시트(HTML) 546 Page - Freescale Semiconductor, Inc |
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546 / 662 page ![]() Application: Date: Programmer: Sheet C 5685X Digital Signal Controller User Manual, Rev. 4 B-44 Freescale Semiconductor Bits Name Description 3 IRQB_STATE State of IRQB This bit reflects the state of the external IRQB 2 IRQA_STATE State of IRQA This bit reflects the state of the external IRQA 1 IRQB_EDG IRQB Edge This bit controls whether the externalIRQB interrupt is edge or level sensitive. Automatically level sensitive during Stop and Wait modes. 0 IRQB interrupt is level sensitive (default) 1 IRQB interrupt is falling edge sensitive 0 IRQA_EDG IRQA Edge This bit controls whether the external IRQA interrupt is edge or level sensitive. Automatically level sensitive during Stop and Wait modes. 0IRQA interrupt is low level sensitive (default) 1IRQA interrupt is falling edge sensitive 24 of 24 ITCN Interrupt Control Register (ICTL) continued IRQ Control Register (ICTL) $1FFF20 + $1A Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read INT IPLC VAB INT_DIS 0 IRQB_STATE IRQA_STATE IRQB_EDG IRQA_ EDG Write Reset 0 0 00 00 00 00 0 0 1 1 0 0 denotes Reserved Bits |
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