DSP56857 datasheet(554/662 Pages) FREESCALE

554 / 662 page

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Date:

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Sheet

5685X Digital Signal Controller User Manual, Rev. 4

B-52

Freescale Semiconductor

8 of 8

DMA

DMA Transfer Control Register (DMATC) continued

Bits

Name

Description

8 - 4

PERIPH SEL

PERIPHERAL SELECT

This bit field selects on of 31 possible DMA peripherals. When the field is equal to 0, operation

begins upon enabling DMA operation. When a peripheral-to-peripheral DMA transfer is desired,

this field should be set to the slower of the two peripherals thereby preventing data overruns.

3 - 2

SS/M

Source Sign/Magnitude

This bit field determines how the DMA Source Address Register gets changed after each DMA

read operation.

Do not change the address register

Increment the address register by data size amount after each read

Decrement the address register by data size amount after each read

1 - 0

DS/M

Destination Sign/Magnitude

This bit field determines how the DMA Destination Address Register gets changed after each

DMA write operation.

Do not change the address register

Increment the address register by data size amount after each read

Decrement the address register by data size amount after each read

denotes Reserved Bits

DMA Transfer

Control Register

(DMATC)

Base + $0

Bits

Read

DMA_ON INTR_ON

INTR_PEND DATA_SIZE

PERIPH SEL

SS/M

DS/M

Write

Reset

00000

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