DSP56857 datasheet(594/662 Pages) FREESCALE

594 / 662 page

Application:

Date:

Programmer:

Sheet

56F853/854/855/857/858 Digital Signal Controller User Manual, Rev. 4

B-92

Freescale Semiconductor

Preliminary

Bits

Name

Description

DIR

Direction

This bit selects either normal count up direction, or the reverse count down direction.

Count up

Count down

EXTINIT

External Initialization

This bit enables another counter/timer within the same module to force the reinitialization of this

counter/timer when the other counter has an active compare event

External counter/timers cannot force a reinitialization of this counter/timer

External counter/timers may force reinitialization of this counter/timer

2 - 0

Output mode

This bit field determines the mode of operation for the OFLAG output signal.

000

Asserted while counter is active

001

Clear OFLAG output on successful compare

010

Set OFLAG output on successful compare

011

Toggle OFLAG output on successful compare

100

Toggle OFLAG output using alternating compare registers

101

Set on compare, cleared on secondary source input edge

110

Set on compare, cleared on counter roll over

111

Enable Gated Clock output while counter is active

TMRA0_CTRL (Timer A, Channel 0 Control)—Address: TMRA_BASE + $6

TMRA1_CTRL (Timer A, Channel 1 Control)—Address: TMRA_BASE + $E

TMRA2_CTRL (Timer A, Channel 2 Control)—Address: TMRA_BASE + $16

TMRA3_CTRL (Timer A, Channel 3 Control)—Address: TMRA_BASE + $1E

TMR Control

$1FFE80 + $6, $E,

$16, $1E

Bits

13 12 11 10

Read

PCS

SCS

ONCE

LENGTH

DIR

EXT

INIT

OM (OFLAG)

Write

Reset

000

TMR

TMR Control Register (CTL) continued

9 of 11

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