DSP56857 datasheet(644/662 Pages) FREESCALE

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Appendix B - Programmer’s Sheets, Rev. 4

Freescale Semiconductor

B-142

Preliminary

HI8

HI8 Command Vector Register (CVR)

Bits

Name

Description

7HC

Host Command

This bit is used by the host processor to handshake the execution of Host Command interrupts.

Normally, the host processor sets HC = 1 to request the Host Command interrupt from the core.

Setting the HC bit causes Host Command pending to be set in the Host Status Register.

6 - 0

CVR Host Vector

These seven bits select the Host Command interrupt offset address in the vector table to be

used by the Host Command interrupt logic. When the Host Command interrupt is recognized by

the DSC interrupt control logic the offset address of the interrupt vector table taken is 2

× HVI0,

6. The Host can write HC and HV in the same write cycle.

6 of 10

HI8 Command

Vector Register

(CVR)

$1FFFD8 + $1

Bits

Read

HV6

HV5

HV4

HV3

HV2

HV1

HV0

Write

Reset

000

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