DSP56857 datasheet(122/662 Pages) FREESCALE

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Clock Generation Concepts

5685X Digital Signal Controller User Manual, Rev. 4

4-14

Freescale Semiconductor

4.7 Clock Generation Concepts

The 568500E system bus is pipelined. The data cycle occurs two system clock cycles after the

address cycle with a between cycle between the two. The SIM also supports two system bus

masters, the core and multi-channel DMA. The SIM contains features to maintain the integrity of

this continuous pipeline during the operation of the system. A hold-off mechanism is furnished to

provide system bus slaves extra clock cycles when needed to maintain synchronization with the

pipeline. A core stall mechanism is provided to keep the 56800E core’s internal pipeline from

advancing when the DMA is master.

The peripheral bus clock has no hold-off, or stall. It runs at one-half the frequency of the system

bus. The peripheral bus reads and writes are single cycle. IPBB is the only master on the

peripheral bus.

A Wait state mechanism permits peripheral bus transactions to take extra cycles when required

by slower peripherals.

The IPBus Bridge (IPBB) coordinates the system and peripheral buses. The IPBB presents

hold-off requests to the system bus pipeline when the system bus transactions generate multiple

peripheral bus transactions, or the peripheral is programmed to generate Wait states.

All generated clocks are true for the first-half period and false for the second-half period. Any

mechanism inhibiting a clock such as hold-off, or core stall, causes the clock to remain low

during the entire period. The CLK_MSTR input can be fed by the PLL output, by the oscillator

running with a crystal, or by the oscillator input being clocked externally. The system bus clock

frequency is always CLK_MSTR/2. The peripheral bus clock frequency is always

CLK_MSTR/4. The CLKOUT frequency is always CLK_MSTR/8.

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