DSP56857 datasheet(136/662 Pages) FREESCALE

136 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

5-10

Freescale Semiconductor

5.6.2.5 Write Wait States (WWS)—Bits 4–0

The WWS field specifies the number of additional system clocks 0-30 (31 is invalid) to delay for

write access to the selected memory. The value of WWS should be set as indicated in

Section 5.7.2.

5.6.3 Chip Select Timing Control Registers 0–3 (CSTC0–CSTC3)

A Chip Select Timing Control (CSTC) register is required for every chip select. This register

specifies the detailed timing required for accessing devices in the selected memory map. At reset,

these registers are configured for minimal timing in the external access waveforms. Therefore,

these registers need only be adjusted if required by slower memory/peripheral devices.

Figure 5-5. Chip Select Timing Control Registers 0–3 (CSTC0–CSTC3)

See Programmer’s Sheet on Appendix page B-12

5.6.3.1 Write Wait States Setup Delay (WWSS)—Bits 15–14

This field affects the write cycle timing diagram, illustrated in Figure 5-16. Additional time

(clock cycles) is provided between the assertion of CSn and address lines and the assertion of

WR. The value of WWSS should be set as indicated in Section 5.7.2.

5.6.3.2 Write Wait States Hold Delay (WWSH)—Bits 13–12

This field affects the write cycle timing diagram, illustrated in Figure 5-17. The WWSH field

specifies the number of additional system clocks to hold the address, data, and CSn signals after

the WR signal is deasserted. The value of WWSH should be set as indicated in Section 5.7.2.

Table 5-5. CSOR Encoding of PS/DS Values

Value

Meaning

Flash_Security_Enable = 0

Flash_Security_Enable = 1

Disable

DS Only

PS Only

Disable

Both PS and DS

DS Only

Base + $10 - $13

Read

WWSS

WWSH

RWSS

RWSH

MDAR

Write

Reset

000

001

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