DSP56857 datasheet(141/662 Pages) FREESCALE

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Timing Specifications

External Memory Interface (EMI), Rev. 4

Freescale Semiconductor

5-15

Note:

INT_SYS_CLK is the internal system clock from which everything is referenced.

Figure 5-9. External Read Cycle with RWS = 1, RWSH = 0 and RWSS = 0

5.7.1.2 Read Setup and Hold Timing

Although most memory devices can perform consecutive reads by holding the CSn and RD(OE)

signals in the active state and changing the address, there are peripheral devices that require

RD(OE) to transition to the inactive state between reads of certain registers. This timing can be

accommodated with the Read Setup (RWSS) and/or Read Hold (RWSH) control fields illustrated

in Figure 5-10 and Figure 5-11.

Time added to Figure 5-8 by setting RWS = 1

tACCESS

tOHZ

tACCESS

tOEV

tRH

tRL

tCSV

tAV

tRDH

tCSRH

tCLKA

tRC

Read (RWS = 1)

IDLE

tRSD

tRSDP

tRSD

tRSDP

tRHD

tRSD

tRSDP

Data In

int_sys_clk

int_sys_clk_delay

A[23:0], PS, DS

CS[7:0]

, OE

D[15:0]

Read (RWS = 1)

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