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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSP56857 데이터시트(PDF) 149 Page - Freescale Semiconductor, Inc |
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DSP56857 데이터시트(HTML) 149 Page - Freescale Semiconductor, Inc |
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149 / 662 page  Resets External Memory Interface (EMI), Rev. 4 Freescale Semiconductor 5-23 Figure 5-17. External Write Cycle with WWS = WWSH = 1 (WWSS = 0) 5.1 Clocks The EMI operates from clocks internal to the chip and does not require/provide clocks external to the chip. 5.1 Interrupts There are no interrupts generated by this module. 5.1 Resets All reset types are equivalent for the EMI and therefore have the same effect. The EMI outputs during reset are controlled by the DRV bit of the BCR. During reset this bit is set to zero. Therefore, Table 5-6 defines the reset state of all EMI pins. tCWL tCWH tCWL tCSV tWDO tWHZ tWDE tWDO tAV tWAC IDLE IDLE Write (WWS = WWSH = 1) IDLE tWRL tDH tDW tWRH tAVW tDW tAVW tWRL tDH tDW tAVW INT_SYS_CLK (core) int_delay_SEMI_clk A[23:0] RD = OE D[16:0] CS2 WR Time added to Figure 5-13 by setting WWSH = 1 tWHZ tDH Write(WWS = WWSH = 1) Write (WWS = WWSH = 1) tAV tCSL tCSV |
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