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STC89LE53RC 데이터시트(PDF) 100 Page - STCmicro Technology Co,.Ltd |
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STC89LE53RC 데이터시트(HTML) 100 Page - STCmicro Technology Co,.Ltd |
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100 / 165 page ![]() ;---------------------------------------------------------------------------------------------------------------------- ; ORL AUXR, #01000000B ;Use Timer 1 in 1T mode ANL AUXR, #10111111B ;Use Timer 1 in 12T mode ;---------------------------------------------------------------------------------------------------------------------- SETB R1 ; Start up Timer 1 SETB ES SETB EA RET ;----------------------------------------------------------------------------------------------------------------------- ;Portal parameter: A= the byte to send Send_One_Byte: ;Send one byte CLR ES CLR TI ;Clear serial port transmit interrupt flag MOV SBUF, A Wait_Send_Finish: JNB TI, Wait_Send_Finish ;Wait to finish send CLR TI SETB ES RET ;------------------------------------------------------------------------------------------------------------------------- END 7.3 Timer/Counter 2 Mode of Operation Timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter as selected by C/T2 in the special function register T2CON. Timer 2 has four operation modes: Capture Mode, Auto-Reload Mode (up or down counting), Baud-Rate Generator Mode and Programable Clock-Out Mode, which are selected by bits T2CON and T2MOD as shown in following table. Timer 2 Operating Modes Table RCLK+TCLK CP/RL2 TR2 Mode 0 0 1 16-bit auto-reload 0 1 1 16-bit capture 1 X 1 buad rate generator X X 0 (off) Capture Mode In the capture mode there are two options selected by bit EXEN2 in T2CON. If EXEN2=0, Timer 2 is a 16-bit timer or counter which upon overflowing sets bit TF2 (Timer 2 overflow flag). This bit can then be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2=1, Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TH2 and TL2, to be captured into registers RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and the EXF2 bit, like TF2, can generate an interrupt which vectors to the same location as Timer 2 overflow interrupt. TF2 and EXF2 is ORed to request the interrupt service. The capture mode is illustrated in following figure. 100 |
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