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GS3471 데이터시트(PDF) 10 Page - Semtech Corporation

부품명 GS3471
상세설명  3G, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer
PDF  179 Pages
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제조업체  SEMTECH [Semtech Corporation]
홈페이지  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

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GS3471
Final Data Sheet Rev.4
PDS-060498
September 2017
10 of 179
Semtech
www.semtech.com
G7
SDOUT
Digital Output
Serial Digital Data Output for the Gennum Serial Peripheral Interface
(GSPI) host control/status port. Active-high output. When GSPI is not
used, leave unconnected.
G8
SCLK
Digital Input
Serial Data Clock input. Burst-mode clock input for the Gennum
Serial Peripheral Interface (GSPI) host control/status port. When GSPI
is not used, SCLK should be tied HIGH or LOW to minimize noise.
H1, H2
AGC, AGC
Analog I/O
Automatic Gain Control for the equalizer. Attach the AGC capacitor
between these pins.
H3
JTAG_EN/DIS
Digital Input,
Internal
Pull-down
JTAG interface reset. Digital active-high to enable JTAG
communications.
When HIGH, JTAG operational mode is enabled.
When LOW, JTAG operational mode is disabled.
H4
WCLK
Output
48kHz word clock for audio. When not used, leave unconnected.
H5
RESET
Digital Input,
Internal Pull-up
Device reset signal.
When LOW, the device will be set to default conditions.
H6
BIT20/BIT10
Digital Input,
Internal Pull-up
Control signal input.
Used to select the output bus width.
HIGH = 20-bit, LOW = 10-bit.
Please refer to the Input Logic parameters in Table 2-3: DC Electrical
Characteristics for logic level threshold and compatibility.
H7
CS
Digital Input
Chip Select input for the Gennum Serial Peripheral Interface (GSPI)
host control/status port. Active-low input. When GSPI is not used,
connect CS to IO_VDD.
J1, J2
DDO_VDD
Power
Power pin for the serial digital output 50Ω buffer. Connect to 1.2V or
1.8V DC analog.
J3
PWR_DWN
Digital Input,
Internal
Pull-down
When HIGH, places the device in a power-down state.
J4,
K4,
J6,
K6
AOUT_1_2,
AOUT_3_4,
AOUT_5_6,
AOUT_7_8
Output
Serial Audio Outputs. When not in use, leave unconnected.
J5
ACLK
Output
64fs sample clock for audio. When not in use, leave unconnected.
K1, K2
DDO, DDO
Digital Output
Differential serial digital outputs. It is possible to DC-couple to
downstream Semtech devices supporting 2.5V inputs. When not in
use, leave unconnected.
K3
AUDIO_EN/DIS
Digital Input,
Internal Pull-up
Control signal input.
When HIGH, enables audio extraction. When LOW, disables audio
extraction.
Please refer to the Input Logic parameters in Table 2-3: DC Electrical
Characteristics for logic level threshold and compatibility.
K5
AMCLK
Output
Oversampled master clock for audio (128fs, 256fs, 512fs selectable).
When not in use, leave unconnected.
Table 1-1: Pin Descriptions (Continued)
Pin Number
Name
Type
Description



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