GS3471 datasheet(98/179 Pages) SEMTECH

98 / 179 page

GS3471

Final Data Sheet Rev.4

PDS-060498

September 2017

98 of 179

Semtech

www.semtech.com

4.22.7 Single Read/Write Access

Single read/write access timing for the GSPI interface is shown in Figure 4-57 to

Figure 4-61.

When performing a single read or write access, one Data Word is read from/written to

the device per access. Each access is a minimum of 32-bits long, consisting of a

Command Word and a single Data Word. The read or write cycle begins with a

high-to-low transition of the CS pin. The read or write access is terminated by a

low-to-high transition of the CS pin.

The inter-command delay time indicated in the figures as tcmd, is a minimum of 3 SCLK

clock cycles. After modifying values in HOST_CONFIG, the inter-command delay time,

tcmd_GSPI_config, is a minimum of 4 SCLK clock cycles.

For read access, the time from the last bit of the Command Word to the start of the data

output, as defined by t5, corresponds to no less than 4 SCLK clock cycles.

Figure 4-57: GSPI Write Timing – Single Write Access with Loop-Through Operation (default)

Figure 4-58: GSPI Write Timing – Single Write Access with GSPI Link-Disable Operation

Figure 4-59: GSPI Write Timing – Single Write Access with Bus-Through Operation

SCLK

SDIN

SDOUT

COMMAND

DATA

COMMAND

cmd

SCLK

SDIN

SDOUT

COMMAND

DATA

COMMAND

cmd

SCLK

SDIN

SDOUT

COMMAND

DATA

High-z

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