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GS3471 데이터시트(PDF) 102 Page - Semtech Corporation

부품명 GS3471
상세설명  3G, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer
PDF  179 Pages
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제조업체  SEMTECH [Semtech Corporation]
홈페이지  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

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GS3471
Final Data Sheet Rev.4
PDS-060498
September 2017
102 of 179
Semtech
www.semtech.com
4.22.10 Default GSPI Operation
By default at power up or after a device reset, the GS3471 is set for Loop-Through
Operation and the internal DEVICE_UNIT_ADDRESS field of the device is set to 0.
Figure 4-67 shows a functional block diagram of the Configuration and Status Register
(CSR) map in the GS3471 for non-extended memory accesses (EMEM = 0).
Figure 4-67: Internal Register Map Functional Block Diagram
The steps required for the application host processor to write to the Configuration and
Status Registers via the GSPI, are as follows:
1. Set Command Word for write access (R/W = 0) to the local registers 0h to 80h; set
Auto Increment; set the Unit Address field in the Command Word to match the
configured DEVICE_UNIT_ADDRESS which will be zero. Write the Command
Word.
2. Write the Data Word to be written to the first register.
3. Write the Data Word to be written to the next register in Auto Increment mode, etc.
Read access is the same as the above with the exception of step 1, where the Command
Word is set for read access (R/W = 1).
Note: The UNIT ADDRESS field of the Command Word must always match
DEVICE_UNIT_ADDRESS for an access to be accepted by the device. Changing
DEVICE_UNIT_ADDRESS to a value other than 0 is only required if multiple devices are
connected to a single chip select (in Loop-Through or Bus-Through configuration.)
[12]
[6:0]
Reg 0
Compare
Configuration and Status Registers
Read/Write
Reg 1
Reg 128
CMD
At power-up or after a device reset, DEVICE_UNIT_ADDRESS = 00
Data to be written / Read Data
DATA
[15:0]
[11:7]
[13]
[14]
bits
Local Address
R / W
Unit Address
BCAST
ALL
Auto
Inc
EMEM
[15]
DEVICE_UNIT_ADDRESS
GSPI_LINK
_DISABLE
GSPI_BUS_
THROUGH
_ENABLE
RESERVED
bits
[4:0]
[13]
[14]
[15]
32 devices
128 registers
bits
RESERVED
[12:5]
h



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