GD25B256DFIS datasheet(35/82 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B256D

7.13.

Quad I/O Fast Read (QIOFR EBH or 4QIOFR ECH)

The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the

3-Byte address (A23-

0) and a “Continuous Read Mode” Byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO2, IO3, and

each bit being latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from

IO0, IO1, IO2, IO3. The first Byte addressed can be at any location. The address is automatically incremented to the next

higher address after each Byte of data is shifted out.

Quad I/O Fast Read with

“Continuous Read Mode”

The Quad I/O Fast Read command can further reduce command overhea

d through setting the “Continuous Read

Mode” bits (M7-0) after the input 3-Byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next

Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. If the

“Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the command code, thus returning

to normal operation. A Reset command can be used to reset (M5-4) before issuing normal command.

Figure 28 Quad I/O Fast Read Sequence Diagram (M5-4

≠ (1, 0), ADS=0)

Note:

1. The dummy clock number is configurable.

Command

EBH

CS#

SCLK

SI(IO0)

SO(IO1)

9 10 11 12 13 14 15

16 17 18 19 20 21 22 23

A23-16 A15-8 A7-0

M7-0

IO2

IO3

Dummy

Byte1 Byte2

GD25B256DFIS 데이터시트(PDF) 35 Page - GigaDevice Semiconductor (Beijing) Inc.