GD25B256DFIS datasheet(38/82 Pages) GIGADEVICE

38 / 82 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B256D

Figure 33 Quad I/O Fast Read with 4-Byte Address Sequence Diagram (M5-4= (1, 0), ADS=0 or ADS=1)

Note:

1. The dummy clock number is configurable.

Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode

The

Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with

Wrap” (77H) commands prior to EBH or ECH. The “Set Burst with Wrap” (77H) command can either enable or disable the

“Wrap Around” feature for the following EBH or ECH commands. When “Wrap Around” is enabled, the data being accessed

can be limited to either an 8/16/32/64-Byte section of a 256-Byte page. The output data starts at the initial address specified

in the command, once it reaches the ending boundary of the 8/16/32/64-Byte section, the output will wrap around the

beginning boundary automatically until CS# is pulled high to terminate the command.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache

afterwards within a fixed length (8/16/32/64-Byte

) of data without issuing multiple read commands. The “Set Burst with Wrap”

command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation

while W6-W5 is used to specify the length of the wrap around section within a page.

7.14.

Set Burst with Wrap (77H)

The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” command to access a fixed

length of 8/16/32/64-Byte section within a 256-Byte page, in standard SPI mode.

The Set Burst with Wrap command sequence: CS# goes low  Send Set Burst with Wrap command  Send 24

dummy bits 

Send 8 bits “Wrap bits”  CS# goes high.

Table 16 Set Burst with Wrap configuration

W6,W5

W4=0

W4=1 (default)

Wrap Around

Wrap Length

Wrap Around

Wrap Length

0, 0

Yes

8-Byte

N/A

0, 1

Yes

16-Byte

N/A

1, 0

Yes

32-Byte

N/A

1, 1

Yes

64-Byte

N/A

If the W6-W4 bits are set by the

Set Burst with Wrap command, all the following “Quad I/O Fast Read” command will

CS#

SCLK

9 10 11 12 13 14 15

SI(IO0)

SO(IO1)

IO2

IO3

A23-16 A15-8 A7-0

M7-0

Dummy

Byte1 Byte2

16 17

A31-24

GD25B256DFIS 데이터시트(PDF) 38 Page - GigaDevice Semiconductor (Beijing) Inc.

GD25B256DFIS 데이터시트(HTML) 38 Page - GigaDevice Semiconductor (Beijing) Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

데이터시트 다운로드

링크 URL