AD9929BBCZ datasheet(58/64 Pages) AD

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AD9929

Rev. A | Page 58 of 64

APPLICATIONS WHERE THE CLI CLOCK FREQUENCY CHANGES DURING OPERATION

The AD9929 must be reset, as described in Figure 69, if the CLI

clock frequency is changed during operation. The DCLK1

output can become unstable if this reset sequence is not applied

after any changes in the CLI clock frequency.

DELAY*

(OUTPUT)

OUTPUTS

OUTCONT

(INTERNAL

SIGNAL)

DIG_STBY

(REGISTER)

SERIAL

WRITES

DCLK1I

HD, VD, H1, (SUBCK = VH2)

FAST

SLOW

(OUTPUT)

(V1, V2, V3, V4 = VL), H2, STROBE, MSHUT

REGION B

REGION A

REGION C

SERIAL PROGRAMMING STEPS MUST BE FOLLOWED WHEN THE CLI CLOCK FREQUENCY CHANGES

1. OUTCONT_REG = 0

2. DIG_STBY = 0

3. DIG_STBY = 1

4. OUTCONT_REG = 1

NOTES ABOUT REGIONS A, B, AND C

1DIGITAL OUTPUTS MAY BECOME INVALID IN REGION A

2DIGITAL OUTPUTS ARE OUTPUT AS SHOWN IN REGION B

3DCLK1 OUTPUT MAY BECOME INVALID IN REGION C

4APPLICATIONS SHOULD NOT USE OUTPUT SIGNALS IN REGION C

t1 = MINIMUM OF 2 CLI CLOCK CYCLES

*IT TAKES 4 CLI CLOCK CYCLES FROM WHEN OUTCONT GOES HIGH UNTIL VD, HD AND DIGITAL OUTPUT DATA IS VALID.

Figure 69. Reset Sequence That Must Be Applied when Changing the CLI Clock Frequency During Operation

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