WM8802SCFV datasheet(17/65 Pages) WOLFSON

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WM8802

PP Rev 1.1 April 2004

OUTPUT CLOCKS (RMCK, RBCK, RLRCK, SBCK, SLRCK)

The WM8802 features two clock systems in order to supply the various clocks for the A/D converter,

DSP and other peripheral devices.

The clock output settings for the R and S systems are set using PRSEL[0:1], XRSEL[0:1],

XRBCK[0:1], XRLRCK[0:1], PSBCK[0:1], PSLRCK[0:1], XSBCK[0:1], and XSLRCK[0:1].

(a)

Setting range for clock output pins when using the PLL source

(1)

RMCK: 1/1, 1/2, and 1/4 of 512fs or 256fs

(2)

RBCK: 64fs output

(3)

RLRCK: fs output

(4)

SBCK: 128fs, 64fs, and 32fs

(5)

SLRCK: 2fs, fs, and fs/2

(b)

Setting range for clock output pins when using the XIN source

(1)

RMCK: 1/1, 1/2, and 1/4 of 12.288MHz or 24.576MHz

(2)

RBCK: 12.288MHz, 6.144MHz, and 3.072MHz

(3)

SBCK: 12.288MHz, 6.144MHz, and 3.072MHz

(4)

RLRCK: 192kHz, 96kHz, and 48kHz

(5)

SLRCK: 192kHz, 96kHz, and 48kHz

The polarity of RBCK, RLRCK, SBCK and SLRCK can be reversed with RBCKP, RLRCKP, SBCKP

and SLRCKP.

Clock switching is processed on the rising edge of the RLRCK output after the falling edge of micro-

controller interface CE.

PLL SOURCE

TMCK

SOURCE

XIN SOURCE

OUTPUT PIN NAME

512fs

256fs

12.288MHz

24.576MHz

512fs

256fs

12.288MHz

24.576MHz

256fs

128fs

6.144MHz

12.288MHz

RMCK

128fs

64fs

3.072MHz

6.144MHz

12.288MHz

64fs

6.144MHz

RBCK

3.072MHz

192kHz

96kHz

RLRCK

48kHz

128fs

12.288MHz

64fs

6.144MHz

SBCK

32fs

3.072MHz

2fs

192kHz

96kHz

SLRCK

fs/2

48kHz

Table 9 Output Clock Frequencies (Bold Items = Initial Settings)

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