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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8802SCFV 데이터시트(PDF) 23 Page - Wolfson Microelectronics plc |
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WM8802SCFV 데이터시트(HTML) 23 Page - Wolfson Microelectronics plc |
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23 / 65 page  Product Preview WM8802 w PP Rev 1.1 April 2004 23 SERIAL AUDIO DATA INPUT/OUTPUT OUTPUT DATA FORMAT (RDATA) The output format is set with OFSEL[0:2]. I 2S is the initial output format setting. Right Justified outputs are only valid in master mode. Output data is output in synchronization with the RLRCK edge immediately after the RERR output becomes Low. LEFT CHANNEL RIGHT CHANNEL RLRCK (0) RBCK (0) RDATA (0) 1/fs n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 LSB MSB 1 BCLK 1 BCLK 16 to 24 bits 16 to 24 bits Figure 12 Data Output Timing – I2S LEFT CHANNEL RIGHT CHANNEL RLRCK (0) RBCK (0) RDATA (0) 1/fs n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 LSB MSB 16 to 24 bits 16 to 24 bits Figure 13 Data Output Timing – Left Justified |
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