WM8802SCFV datasheet(28/65 Pages) WOLFSON

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WM8802

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PP Rev 1.1 April 2004

PLL LOCK ERROR

The PLL becomes unlocked for input data that has lost bi-phase modulation regularity or input data

where preambles B, M, and W cannot be detected.

RERR goes High during the occurrence of a PLL lock error and returns to Low when data

demodulation returns to normal. High is maintained between 45ms and 300ms.

The rising and falling edges of RERR are synchronized with RLRCK.

INPUT DATA PARITY ERROR

Input parity errors are detected if there are an odd number of parity bits in input data.

RERR goes High indicating that the PLL is locked if an input parity error occurs 9 or more times in

succession, It returns to Low after being High for between 45ms and 300ms.

The error flag output format, for when an input parity error is output 8 times in succession, can be

selected using REDER.

OTHER ERRORS

The channel status bits 24 to 27 (sampling frequency) are always read and the data of the previous

block is compared with the current data, even if RERR goes Low. The input data sampling frequency

is also calculated from the fs clock extracted from the input data and fs calculation value comparison

is performed as described above. RERR is instantly made High if a difference is detected, and the

same processing as for PLL lock errors is performed.

The PLL causes a lock error when the sampling frequency changes as described above. FSERR can

be set to support sources with a variable sampling frequency (for example a CD player with a

variable pitch function). No error flag is output if the sampling frequency variation falls within the PLL

capture range while using FSERR.

For input data within the reception range, FSERR prevents fs calculation results from being reflected

in the error flag that is set using FSLIM[0:1]. RERR goes Low if the PLL status changes to the locked

status.

RERR changes to a High output upon detection of non-PCM data input if RESEL is set. The PLL

locked status and various output clocks continue to be output according to the input data but the

output data is muted.

DATA PROCESSING UPON ERROR OCCURRENCE (LOCK ERROR, PARITY

ERROR)

The data processing after the occurrence of an error is described below. If 8 or fewer input parity

errors occur in succession transfer data is replaced by the data saved to L-ch and R-ch in the

previous frame of PCM audio data. The error data is output as it is if the transfer data is non-PCM

data. Non-PCM data is based on data detected prior to occurrence of an input parity error when bit 1

of the channel status goes High.

Output data is muted upon occurrence of a PLL lock error or when a parity error occurs 9 or more

times in succession.

For the channel status, the data of the previous block is held in 1-bit units when a parity error occurs.

WM8802SCFV 데이터시트(PDF) 28 Page - Wolfson Microelectronics plc