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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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V62/12615-01XE-R 데이터시트(PDF) 17 Page - Texas Instruments |
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V62/12615-01XE-R 데이터시트(HTML) 17 Page - Texas Instruments |
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17 / 98 page  TX_CLK TX_EN TXD PMD output pair (J/K) T2.6.1 IDLE DATA RX_CLK RXD[3:0] RX_DV RX_ER Valid data T2.5.2 T2.5.1 T2.5.1 17 DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Submit Documentation Feedback Product Folder Links: DP83848-EP Specifications Copyright © 2012–2019, Texas Instruments Incorporated 4.7.5 100-Mbps MII Receive Timing PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.5.1 RX_CLK high/low time 100-Mbps Normal mode 16 20 24 ns T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER delay 100-Mbps Normal mode 10 30 ns (1) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100-Mbps mode. Figure 4-6. 100-Mbps MII Receive Timing 4.7.6 100BASE-TX Transmit Packet Latency Timing PARAMETER DESCRIPTION NOTES(1) MIN TYP MAX UNIT T2.6.1 TX_CLK to PMD output pair latency 100-Mbps Normal mode 6 bits Figure 4-7. 100BASE-TX Transmit Packet Latency Timing |
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