V62SLASH12615-01XE-R datasheet(20/98 Pages) TI1

20 / 98 page

(T/R)

IDLE

DATA

PMD input pair

CRS

T2.10.1

(J/K)

IDLE

DATA

PMD input pair

CRS

RXD[3:0]

RX_DV

RX_ER

T2.9.1

T2.9.2

DP83848-EP

SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Product Folder Links: DP83848-EP

Specifications

(1)

Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.

(2)

1 bit time = 10 ns in 100-Mbps mode.

(3)

PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.

4.7.9

100BASE-TX Receive Packet Latency Timing

PARAMETER

DESCRIPTION(1)

NOTES(2) (3)

MIN

TYP

MAX

UNIT

T2.9.1

Carrier sense ON delay

100-Mbps Normal mode

bits

T2.9.2

Receive data latency

100-Mbps Normal mode

bits

(1)

Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.

(2)

1 bit time = 10 ns in 100-Mbps mode.

Figure 4-10. 100BASE-TX Receive Packet Latency Timing

4.7.10 100BASE-TX Receive Packet Deassertion Timing

PARAMETER

DESCRIPTION

NOTES(1) (2)

MIN

TYP

MAX

UNIT

T2.10.1

Carrier sense OFF delay

100-Mbps Normal mode

bits

Figure 4-11. 100BASE-TX Receive Packet Deassertion Timing

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