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V62/12615-01XE-R 데이터시트(PDF) 51 Page - Texas Instruments

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부품명 V62/12615-01XE-R
상세설명  DP83848-EP PHYTER??Military Temperature Single Port 10/100 Mbps Ethernet Physical Layer Transceiver
PDF  98 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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V62/12615-01XE-R 데이터시트(HTML) 51 Page - Texas Instruments

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DP83848-EP
www.ti.com
SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019
Submit Documentation Feedback
Product Folder Links: DP83848-EP
Detailed Description
Copyright © 2012–2019, Texas Instruments Incorporated
5.5.1.3.1.1 Half Duplex Mode
In Half Duplex mode the DP83848-EP functions as a standard IEEE 802.3 10BASE-T transceiver
supporting the CSMA/CD protocol.
5.5.1.3.1.2 Full Duplex Mode
In Full Duplex mode the DP83848-EP can simultaneously transmit and receive without asserting the
collision signal. The 10-Mbps ENDEC is designed to encode and decode simultaneously.
5.5.1.3.2 Smart Squelch
The smart squelch is responsible for determining when valid data is present on the differential receive
inputs. The DP83848-EP implements an intelligent receive squelch to ensure that impulse noise on the
receive inputs will not be mistaken for a valid signal. Smart squelch operation is independent of the
10BASE-T operational mode.
The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the
IEEE 802.3 10BSE-T standard) to determine the validity of data on the twisted-pair inputs (see Figure 5-
9).
The signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the
squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch
level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. Finally the
signal must again exceed the original squelch level within 150 ns to ensure that the input waveform will
not be rejected. This checking procedure results in the loss of typically three preamble bits at the
beginning of each packet.
Only after all these conditions have been satisfied will a control signal be generated to indicate to the
remainder of the circuitry that valid data is present. At this time, the smart squelch circuitry is reset.
Valid data is considered to be present until the squelch level has not been generated for a time longer
than 150 ns, indicating the End of Packet. Once good data has been detected, the squelch levels are
reduced to minimize the effect of noise causing premature End of Packet detection.
Figure 5-9. 10BASE-T Twisted-Pair Smart Squelch Operation
5.5.1.3.3 Collision Detection and SQE
When in Half Duplex, a 10BASE-T collision is detected when the receive and transmit channels are active
simultaneously. Collisions are reported by the COL signal on the MII. Collisions are also reported when a
jabber condition is detected.
The COL signal remains set for the duration of the collision. If the PHY is receiving when a collision is
detected it is reported immediately (through the COL pin).



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