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STR720RBQ6 데이터시트(PDF) 63 Page - STMicroelectronics

부품명 STR720RBQ6
상세설명  ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES
PDF  401 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STR720RBQ6 데이터시트(HTML) 63 Page - STMicroelectronics

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STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)
63/401
Interrupt Pending Register 0 (IPR0)
Address Offset: 40h
Reset value: 0000 0000h
Bit 31= IPR[31]: Channel 31 Interrupt Pending bit
Bit 30 = IPR[30]: Channel 30 Interrupt Pending bit
...
Bit 1 = IPR[1]: Channel 1 Interrupt Pending bit
Bit 0 = IPR[0]: Channel 0 Interrupt Pending bit
The IPR0 is a 32 bit register: it provides a pending bit for each of the 32 EIC interrupt input
channels.
This is where actually the information about the channel interrupt status is kept: if the
corresponding bit in the enable register IER0 has been set, the IPR0 bit set high (active)
means that the related channel has asserted an interrupt request that has not been serviced
yet.
The bits are Read/Clear, i.e. writing a ‘0’ has no effect, whereas writing a ‘1’ clears the bit
(forces it to ‘0’).
1: Interrupt pending
0: No interrupt pending
Note
Before exiting the ISR (Interrupt Service Routine), the software must be sure to have
cleared the EIC IPR0 bit related to the executed routine: this bit clear will be read by
the EIC logic as End of Interrupt (EOI) sequence, and will allow the interrupt stack
pop and new interrupts processing .
31
30
29
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27
26
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24
23
22
21
20
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17
16
IPR[31:16]
rc
15
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9
8
765432
1
0
IPR[15:0]
rc
1



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