STR720RBQ6 datasheet(94/401 Pages) STMICROELECTRONICS

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STR720 - DMA CONTROLLER (DMAC)

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Terminal Counter Register X (DMATCntX) (X=2,3)

Address Offset: A8h - E8h

Reset value: 0000h

DMATCntX contains the number of data units remaining in the current DMA transfer. The data

unit is equal to the DMA data with (byte, half-word or word) configured for the source side, if

Dir bit of DMACtrlX register is 0, or for the destination side, if Dir bit of DMACtrlX register is 1.

The register value is decremented every time data is transferred to the DMA FIFO. When the

Terminal Count reaches zero, the FIFO content is transferred to the Destination and the DMA

transfer is finished. This is a read only register.

Bit 15:0 = DMATCntX[15:0]

Note

DMATCntX register can be used also in Circular buffer mode, with the exception of

the last buffer sweep. Once LAST flag is set, the value of DMATCntX register

becomes not meaningful and should be ignored.

Last Used Buffer location X (DMALUBuffX) (X=2,3)

Address Offset: ACh - ECh

Reset value: 0000h

DMALUBuffX is used in circular buffer mode during last buffer sweep, and it contains the

circular buffer position where the last data to be used by stream X is located. The first buffer

location is indicated writing 0x0000 into this register, the second with 0x0001 and so on, up to

the last location which is indicated setting this register with (DMAMaxX - 1). For a description

of this register usage, see also Circular mode operations on page 84

Bit 15:0 = DMALUBuffX[15:0]

765432

DMATCntX

765432

DMALUBuff

STR720RBQ6 데이터시트(PDF) 94 Page - STMicroelectronics