| 전자부품 데이터시트 검색엔진 |
|
STR720RBQ6 데이터시트(PDF) 51 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STR720RBQ6 데이터시트(HTML) 51 Page - STMicroelectronics |
|
51 / 401 page ![]() STR720 - ENHANCED INTERRUPT CONTROLLER (EIC) 51/401 7 ENHANCED INTERRUPT CONTROLLER (EIC) 7.1 Introduction The ARM720T CPU provides two levels of interrupt, FIQ (Fast Interrupt Request) for fast, low latency interrupt handling and IRQ (Interrupt Request) for more general interrupts. Hardware handling of multiple interrupt channels, interrupt priority and automatic vectorization require therefore a separate Enhanced Interrupt Controller (EIC). 7.2 Main Features ■ 32 maskable interrupt channels, mapped on ARM’s interrupt request pin IRQ ■ 16 programmable priority levels for each interrupt channels mapped on IRQ ■ hardware support for interrupt nesting (16 levels) ■ 3 maskable interrupt channels, mapped on ARM’s interrupt request pin FIQ, with neither priority nor vectorization Figure 7. EIC block diagram IRQ0 IRQ1 IRQ31 IER0-IER1 FIQ0 FIQ1 FIR FIQ control logic IRQ control logic FIQ request IRQ request STACK CTL (PUSH/POP) PRIORITY STACK (16 ENTRY) CIPR FIQ to ARM720T Highest Priority Interrupt SIR (32 ENTRY) IRQx VECTOR IE0 IE1 IE31 IP0 IP1 IP31 IPR0-IPR1 FIE[0] FIE[1] FIR FIP[0] FIP[1] IRQ_EN ICR FIQ_EN SIRn(31:16) IVR(31:16) Interrupt from line IRQx IVR IRQ to ARM720T FIE[2] FIP[2] FIQ2 1 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |