STR720RBQ6 datasheet(101/401 Pages) STMICROELECTRONICS

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STR720 - DRAM CONTROLLER (DRAMC)

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10 DRAM CONTROLLER (DRAMC)

10.1 Introduction

The DRAM Controller block is an AHB slave used to provide an interface between the system

bus and external memory devices. The memory clock frequency is the same as the system

bus clock frequency.

The controller supports four external banks, containing either SDRAM or EDO memories; all

banks must be of the same memory type. Each bank can be independently configured and

enabled/disabled by means of internal configuration registers.

All the internal registers are accessed via an Advanced Peripheral Bus interface (APB) to the

DRAM Controller.

A refresh timer is provided to issue refresh commands to the memory; such refresh counter

uses the CLK input signal prescaled by 16 in order to trigger the refresh events.

10.2 Main Features

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8, 16 or 32 bits for the memory data bus width.

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4 external memory banks.

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It is possible to use less than four banks, but banks must be contiguous.

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Each bank can span from 64 kBytes up to 32 MBytes in 64 kBytes increments.

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128 MBytes of total addressable external memory space, when all banks have the maximum

size.

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Little endian operations supported.

10.3 Functional Description

10.3.1

AHB Interface

The DRAM Controller is a configurable peripheral devoted to manage an external memory

component. The AHB Interface decomposes the system bus transfers into memory accesses

supported by the selected memory bank and performs the data transfers to/from the external

chip. At the end of each access it will execute DRAM precharge, i.e. the SDRAM banks are

not kept open.

It supports up to 4 memory banks, where a bank is one single memory chip or more chips that

share the same addresses and chip select. If a disabled memory bank is accessed, the

Controller will return the ERROR response, otherwise it will return the OKAY response.

External memory transfers are configurable to be 8,16 or 32-bit wide.

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