STR720RBQ6 datasheet(110/401 Pages) STMICROELECTRONICS

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STR720 - DRAM CONTROLLER (DRAMC)

110/401

Memory Configuration Register (MemConfig)

Address Offset: 30h

Reset value: 0000h

The Memory Configuration Register (MemConfig) is a 16-bit read/write control register used

to configure parameters that are the same for all banks.

The MemConfig control bits are described below.

Bit 15:14 reserved (should be written as zero and ignored on read ).

Bit 13

PWRSAVE: Power Save Mode.

This bit selects whether to enter the power save self-refresh mode.

= 1. The next refresh cycle will set the memory devices in the self-refresh mode.

= 0. Next refresh cycle the memories will exit the self-refresh mode.

Bit 12

TYPE: Memory Type.

This bit selects the type of the external memory.

= 1. SDRAM.

= 0. EDO.

Bit 11

B4EN: Bank 4 Enable.

This bit enables Bank 4 of memory.

= 1. Bank enabled.

= 0. Bank disabled.

Bit 10

B3EN: Bank 3 Enable.

This bit enables Bank 3 of memory.

= 1. Bank enabled.

= 0. Bank disabled.

Bit 9

B2EN: Bank 2 Enable.

This bit enables Bank 2 of memory.

= 1. Bank enabled.

= 0. Bank disabled.

Bit 8

B1EN: Bank 1 Enable.

This bit enables Bank 1 of memory.

= 1. Bank enabled.

= 0. Bank disabled.

Bit 7:0

REFR[7:0]: Refresh Period.

This field is used to determine the refresh period. The refresh period can be set in

6543210

reserved

PWRSAVE TYPE

B4EN

B3EN

B2EN

B1EN

REFR[7:0]

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