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SSD1963QL9 데이터시트(PDF) 19 Page - List of Unclassifed Manufacturers

부품명 SSD1963QL9
상세설명  1215KB Embedded Display SRAM LCD Display Controller
PDF  93 Pages
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제조업체  ETC2 [List of Unclassifed Manufacturers]
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SSD1963QL9 데이터시트(HTML) 19 Page - List of Unclassifed Manufacturers

Back Button SSD1963QL9 Datasheet HTML 15Page - List of Unclassifed Manufacturers SSD1963QL9 Datasheet HTML 16Page - List of Unclassifed Manufacturers SSD1963QL9 Datasheet HTML 17Page - List of Unclassifed Manufacturers SSD1963QL9 Datasheet HTML 18Page - List of Unclassifed Manufacturers SSD1963QL9 Datasheet HTML 19Page - List of Unclassifed Manufacturers SSD1963QL9 Datasheet HTML 20Page - List of Unclassifed Manufacturers SSD1963QL9 Datasheet HTML 21Page - List of Unclassifed Manufacturers SSD1963QL9 Datasheet HTML 22Page - List of Unclassifed Manufacturers SSD1963QL9 Datasheet HTML 23Page - List of Unclassifed Manufacturers Next Button
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 19 / 93 page
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SSD1963
Rev 1.1
P 19/93
Jan 2010
Solomon Systech
Figure 7-2: Clock Control Diagram
7.3
Frame Buffer
There are 1215K bytes built-in SRAM inside SSD1963 to use as frame buffer. When the frame buffer is
written or read, the “address counter” will automatically increase by one or decrease by one depends on the
frame buffer settings.
Table 7-2: Frame Buffer Settings regarding to set_address_mode command 0x36
7.4
System Clock and Reset Manager
The “System Clock and Reset Manager” distributes the reset signal and clock signal to the entire system. It
controls the Clock Generator and contains clock gating circuitry to turn on and off the clock of each
functional module. Also, it divides the root clock from Clock Generator to operation clocks for different
module. The System Clock and Reset Manager also manage the reset signals to ensure all the module are
reset to appropriate status when the system are in reset state, deep sleep state, sleep state and display state.
Figure 7-3 shows a state diagram of four operation states of SSD1963.
1/N
1/M
CLK
PLL
REF
FB
1
0
set_pll bit 1
System Clock
OSC
XTAL_IN
XTAL_OUT
EXTERNAL
CRYSTAL
EN
set_pll bit 0



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