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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CC3235MODASF 데이터시트(PDF) 58 Page - Texas Instruments |
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CC3235MODASF 데이터시트(HTML) 58 Page - Texas Instruments |
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58 / 100 page  T2 T3 T4 T7 T8 T7 T8 T9 T10 T9 T10 T1 T11 TDI Input Valid TDO Output Valid TDO Output Valid TMS Input Valid TDI Input Valid TCK TMS TDI TDO TMS Input Valid 58 CC3235MODAS, CC3235MODASF SWRS233 – OCTOBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: CC3235MODAS CC3235MODASF Specifications Copyright © 2019, Texas Instruments Incorporated 5.19.5.5 IEEE 1149.1 JTAG The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and boundary scan architecture for digital integrated circuits and provides a standardized serial interface to control the associated test logic. For detailed information on the operation of the JTAG port and TAP controller, see the IEEE Standard 1149.1,Test Access Port and Boundary-Scan Architecture. Figure 5-14 shows the JTAG timing diagram. Figure 5-14. JTAG Timing Diagram Table 5-21 lists the JTAG timing parameters. Table 5-21. JTAG Timing Parameters ITEM NAME DESCRIPTION MIN MAX UNIT T1 fTCK Clock frequency 15 MHz T2 tTCK Clock period 1 / fTCK ns T3 tCL Clock low period tTCK / 2 ns T4 tCH Clock high period tTCK / 2 ns T7 tTMS_SU TMS setup time 1 ns T8 tTMS_HO TMS hold time 16 ns T9 tTDI_SU TDI setup time 1 ns T10 tTDI_HO TDI hold time 16 ns T11 tTDO_HO TDO hold time 15 ns |
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