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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LPC47M14X 데이터시트(PDF) 192 Page - SMSC Corporation |
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LPC47M14X 데이터시트(HTML) 192 Page - SMSC Corporation |
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192 / 205 page  SMSC DS – LPC47M14X Page 192 Rev. 03/19/2001 t2 t1 t5 t6 t4 t3 t4 PD<7:0> nACK nALF FIGURE 34 – ECP PARALLEL PORT REVERSE TIMING NAME DESCRIPTION MIN TYP MAX UNITS t1 PDATA Valid to nACK Asserted 0 ns t2 nALF Deasserted to PDATA Changed 0 ns t3 nACK Asserted to nALF Deasserted (Notes 1,2) 80 200 ns t4 nACK Deasserted to nALF Asserted (Note 2) 80 200 ns t5 nALF Asserted to nACK Asserted 0 ns t6 nALF Deasserted to nACK Deasserted 0 ns Note 1: Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can stall by keeping nALF low. Note 2: nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. |
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