LPC47M14X datasheet(35/205 Pages) SMSC

35 / 205 page

SMSC DS – LPC47M14X

Page 35

Rev. 03/19/2001

An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current

sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result

phase may be entered.

Table 12 – FIFO Service Delay

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING AT

2 Mbps DATA RATE

1 byte

2 bytes

8 bytes

15 bytes

1 x 4

µs - 1.5 µs = 2.5 µs

2 x 4

µs - 1.5 µs = 6.5 µs

8 x 4

µs - 1.5 µs = 30.5 µs

15 x 4

µs - 1.5 µs = 58.5 µs

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING AT

1 Mbps DATA RATE

1 byte

2 bytes

8 bytes

15 bytes

1 x 8

µs - 1.5 µs = 6.5 µs

2 x 8

µs - 1.5 µs = 14.5 µs

8 x 8

µs - 1.5 µs = 62.5 µs

15 x 8

µs - 1.5 µs = 118.5 µs

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING AT

500 Kbps DATA RATE

1 byte

2 bytes

8 bytes

15 bytes

1 x 16

µs - 1.5 µs = 14.5 µs

2 x 16

µs - 1.5 µs = 30.5 µs

8 x 16

µs - 1.5 µs = 126.5 µs

15 x 16

µs - 1.5 µs = 238.5 µs

DIGITAL INPUT REGISTER (DIR)

Address 3F7 READ ONLY

This register is read-only in all modes.

PC-AT Mode

BIT 0 - 6 UNDEFINED

The data bus outputs D0 - 6 are read as ‘0’.

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value

programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).

PS/2 Mode

DSK

CHG

RESET

COND.

N/A

DSK

CHG

DRATE

SEL1

DRATE

SEL0

nHIGH

DENS

RESET

COND.

N/A

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