전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

USB333X 데이터시트(PDF) 63 Page - Microchip Technology

부품명 USB333X
상세설명  Industry?셲 Smallest Hi-Speed USB Transceiver with Single Supply Operation
PDF  85 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

USB333X 데이터시트(HTML) 63 Page - Microchip Technology

Back Button USB333X Datasheet HTML 59Page - Microchip Technology USB333X Datasheet HTML 60Page - Microchip Technology USB333X Datasheet HTML 61Page - Microchip Technology USB333X Datasheet HTML 62Page - Microchip Technology USB333X Datasheet HTML 63Page - Microchip Technology USB333X Datasheet HTML 64Page - Microchip Technology USB333X Datasheet HTML 65Page - Microchip Technology USB333X Datasheet HTML 66Page - Microchip Technology USB333X Datasheet HTML 67Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 63 / 85 page
background image
 2009 - 2015 Microchip Technology Inc.
DS00001880A-page 63
USB333x
7.1.1.11
USB Interrupt Latch
Address = 14h (read only with auto clear)
Note 7-3
rd: Read Only with auto clear.
7.1.1.12
Debug
Address = 15h (read only)
7.1.1.13
Scratch Register
Address = 16-18h (read), 16h (write), 17h (set), 18h (clear)
Field Name
Bit
Access
Default
Description
HostDisconnect Latch
0
rd
(Note 7-3)
0b
Set to 1b by the PHY when an unmasked event
occurs on Hostdisconnect. Cleared when this register
is read. Applicable only in host mode.
VbusValid Latch
1
0b
Set to 1b by the PHY when an unmasked event
occurs on VbusValid. Cleared when this register is
read.
SessValid Latch
2
0b
Set to 1b by the PHY when an unmasked event
occurs on SessValid. Cleared when this register is
read.
SessEnd Latch
3
0b
Set to 1b by the PHY when an unmasked event
occurs on SessEnd. Cleared when this register is
read.
IdGnd Latch
4
0b
Set to 1b by the PHY when an unmasked event
occurs on IdGnd. Cleared when this register is read.
Reserved
7:5
rd
0h
Read only, 0.
Field Name
Bit
Access
Default
Description
Linestate[1:0]
1:0
rd
00b
Contains the current value of Linestate[1:0].
Reserved
7:2
rd
000000b
Read only, 0.
Field Name
Bit
Access
Default
Description
Scratch
7:0
rd/w/s/c
00h
Empty register byte for testing purposes. Software
can read, write, set, and clear this register and the
PHY functionality will not be affected.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com