USB333X datasheet(13/85 Pages) MICROCHIP

13 / 85 page

 2009 - 2015 Microchip Technology Inc.

DS00001880A-page 13

USB333x

DATA[5]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

DATA[4]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

CLKOUT

Output,

CMOS

N/A

ULPI Clock Out Mode:

60MHz ULPI clock output. All ULPI signals are driven

synchronous to the rising edge of this clock.

ULPI Clock In Mode:

Connect this pin to VDDIO to configure 60MHz ULPI

Clock IN mode as described in Section 5.4.1.

DATA[3]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

DATA[2]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

DATA[1]

I/O,

CMOS

N/A

ULPI bi-directional data bus.

DATA[0]

I/O,

CMOS

N/A

ULPI bi-directional data bus. DATA[0] is the LSB.

NXT

Output,

CMOS

High

The PHY asserts NXT to throttle the data. When the

Link is sending data to the PHY, NXT indicates when

the current byte has been accepted by the PHY.

DIR

Output,

CMOS

N/A

Controls the direction of the data bus. When the PHY

has data to transfer to the Link, it drives DIR high to

take ownership of the bus. When the PHY has no data

to transfer it drives DIR low and monitors the bus for

commands from the Link.

STP

Input,

CMOS

High

The Link asserts STP for one clock cycle to stop the

data stream currently on the bus. If the Link is sending

data to the PHY, STP indicates the last byte of data

was on the bus in the previous cycle.

VDD18

Power

N/A

1.8V Regulator Output. A 1.0uF (<1 ohm ESR) bypass

capacitor to ground is required for regulator stability.

The bypass capacitor should be placed as close as

possible to the USB333x.

RESETB

Input,

CMOS,

Low

When low, the part is suspended and the 3.3V and

1.8V regulators are disabled. When high, the

USB333x will operate as a normal ULPI device, as

described in Section 5.5.1. The state of this pin may

be changed asynchronously to the clock signals.

When asserted for a minimum of 1 microsecond and

then de-asserted, the ULPI registers are reset to their

default state and all internal state machines are reset.

REFCLK

Input,

CMOS

N/A

ULPI Clock Out Mode:

Frequency set by REF[0] pin.

ULPI Clock In Mode:

60MHz ULPI clock input.

RBIAS

Analog,

CMOS

N/A

Bias Resistor pin. This pin requires an 8.06kΩ (±1%)

resistor to ground, placed as close as possible to the

USB333x. Nominal voltage during ULPI operation is

0.8V.

GND

Ground

N/A

Ground.

TABLE 2-3:

USB3333 PIN DESCRIPTION (CONTINUED)

Ball

Name

Direction/

Type

Active

Level

Description

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