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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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T1024 데이터시트(PDF) 37 Page - Freescale Semiconductor, Inc |
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T1024 데이터시트(HTML) 37 Page - Freescale Semiconductor, Inc |
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37 / 49 page  CPLD_HWVER field descriptions Field Description 0–7 HW_VER Hardware version. The version field of the hardware board. 3.1.4 Software Version Register (CPLD_SWVER) Address: 0h base + 3h offset = 3h Bit 0 1 2 3 4 5 6 7 Read SW_VER Write Reset x* x* x* x* x* x* x* x* * Notes: x depends on actual board setting.x = Undefined at reset. • CPLD_SWVER field descriptions Field Description 0–7 SW_VER 3.1.5 Reset Control Register (CPLD_RSTCON) Address: 0h base + 10h offset = 10h Bit 0 1 2 3 4 5 6 7 Read SW_RST DDR_RST EC1_RST EC2_RST Reserved XGT1_RST XGT2_RST Write w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 CPLD_RSTCON field descriptions Field Description 0 SW_RST 0 No reset occurs 1 Write a logic 1 will produce whole board reset# signal, this bit can auto clear. 1 DDR_RST 0 No reset occurs 1 Write a logic 1 will produce DDR3 reset# signal, this bit can auto clear. 2 EC1_RST 0 No reset occurs. 1 Write a logic 1 will produce RGMII PHY1(RTL82111E-VB) reset# signal, this bit can auto clear. 3 EC2_RST 0 No reset occurs. 1 Write a logic 1 will produce RGMII PHY2(RTL82111E-VB) reset# signal, this bit can auto clear. Table continues on the next page... Chapter 3 CPLD Specification QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015 Freescale Semiconductor, Inc. 37 |
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