T1024 datasheet(6/49 Pages) FREESCALE

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Table 1-1. Useful references (continued)

Document

Description

QorIQ Data Path Acceleration

Architecture (DPAA) Reference

Manual (DPAARM)

Describes the core set of DPAA functionality implemented in many QorIQ chips, and

identifies those portions of the DPAA whose implementation varies from chip to chip.

The QorIQ data path acceleration architecture (DPAA) provides the infrastructure to

support simplified sharing of networking interfaces and accelerators by multiple CPU

cores. These resources are abstracted into enqueue/dequeue operations by means of

a common DPAA Queue Manager (QMan) driver.

1.2 Acronyms and abbreviations

The table below lists and explains the acronyms and abbreviations used in this document.

Table 1-2. Acronyms and abbreviations

Usage

Description

COP

Common On-chip Processor

CPC

CoreNet Platform Cache

CPLD

Complex Programmable Logic Device

DIMM

Dual In-Line Memory Module

DIP

Dual In-Line Package

DIU

Display Interface Unit

DMA

Direct Memory Access

DPAA

Data Path Acceleration Architecture

DRAM

Dynamic Random Access Memory

DUT

Device Under Test

Ethernet Controllers

EDC

Error Detection and Correction

EEPROM

Electrically Erasable Programmable Read-Only Memory

EMI

Ethernet Management Interfaces

eMMC

embedded MultiMediaCard

eSDHC

enhanced Secure Digital Host Controller

eSPI

enhanced Serial Peripheral Interface

FET

Field Effect Transistor

HDLC

High-level Data Link Control

I2C

Inter-Integrated Circuit

IFC

Integrated Flash Controller

JTAG

Joint Test Action Group

MPIC

Multicore Programmable Interrupt Controller

PCIe/PEX

PCI Express

PLD

Programmable Logic Device

POR

Power On Reset

Table continues on the next page...

Acronyms and abbreviations

QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015

Freescale Semiconductor, Inc.

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