T1024 datasheet(12/49 Pages) FREESCALE

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NOTE

1. Set RGMII limits to LVDD=2.5 V.

2. Supply PROG_SFP/PROG_MTR with 1.8 V only during

the secure boot fuse programming.

2.3 Deep sleep control

The T1024 processor has the ability to enter into the deep-sleep mode. Once the

processor has readied itself for the deep-sleep mode, setting the CPLD register

PWR_CTL[SLP] = 1 causes the power sequencer to begin an orderly shutdown of several

power supplies, while others remain active.

Once ready, PWR_MSTAT[STATE] will indicate the system is asleep. However, the

processor is already in the idle state, so this may not be needed by the system software.

Perform the following steps to send the T1024 processor to the deep-sleep mode:

• Prepare the CPLD to ignore the external signals. For example, some interrupt pins

will power down, so the CPLD masks these pins from presenting valid interrupts.

• Prepare the DDR subsystem for self-refresh by forcing RST_MEM_B high, forcing

the CKE# “clamp” FETs low.

• Gate the secondary powers to the DUT. Any power supply marked as “sleeps” in the

power section diagrams are enable-disable, or can be gated.

Once the above steps are completed, the system enters into the deep-sleep mode. The

system software has the timers or interrupt controllers programmed such that important

events can wake the processor (which will be powered only by VDDC) and can decide if

situations warrant returning to sleep, or activating full power.

2.4 Reset

The CPLD manages the reset signals to and from the T1024 processor and other devices

on the T1024RDB. The following figure shows an overview of the reset architecture.

Deep sleep control

QorIQ T1024 Reference Design Board User Guide, Rev. 0, 04/2015

Freescale Semiconductor, Inc.

T1024 데이터시트(PDF) 12 Page - Freescale Semiconductor, Inc