STM32F722IC datasheet(45/229 Pages) STMICROELECTRONICS

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DS11853 Rev 6

45/229

STM32F722xx STM32F723xx

Functional overview

SAI1 and SAI2 can be served by the DMA controller

3.25

Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows

to achieve an error-free I2S sampling clock accuracy without compromising on the CPU

performance, while using USB peripherals.

The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change

without disabling the main PLL (PLL) used for CPU and USB interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging

from 8 KHz to 192 KHz.

In addition to the audio PLL, a master clock input pin can be used to synchronize the

I2S/SAI flow with an external PLL (or Codec output).

3.26

Audio PLL (PLLSAI)

An additional PLL dedicated to audio is used for the SAI1 peripheral in case the PLLI2S is

programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz)

and the audio application requires both sampling frequencies simultaneously.

3.27

SD/SDIO/MMC card host interface (SDMMC)

SDMMC host interfaces are available, that support MultiMediaCard System Specification

Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory

Card Specification Version 2.0.

The SDMMC Card Specification Version 2.0 is also supported with two different databus

modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a

stack of MMC4.1 or previous.

The SDMMC can be served by the DMA controller

3.28

Controller area network (bxCAN)

The CAN is compliant with the 2.0A and B (active) specifications with a bit rate up to 1

Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as

extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive

FIFOs with 3 stages and 28 shared scalable filter banks (all of them can be used even if one

CAN is used). 256 bytes of SRAM are allocated to the CAN.

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