STM32F722IC datasheet(167/229 Pages) STMICROELECTRONICS

167 / 229 page

DS11853 Rev 6

167/229

STM32F722xx STM32F723xx

Electrical characteristics

201

Figure 53. SPI timing diagram - slave mode and CPHA = 0

tsu(MI)

Data input setup time

Master mode

tsu(SI)

Slave mode

3.5

th(MI)

Data input hold time

Master mode

th(SI)

Slave mode

ta(SO)

Data output access time

Slave mode

tdis(SO)

Data output disable time

Slave mode

tv(SO)

Data output valid time

Slave mode 2.7≤VDD≤3.6V

6.5

Slave mode 1.71≤VDD≤3.6V

6.5

13.5

tv(MO)

Master mode

th(SO)

Data output hold time

Slave mode

1.71≤VDD≤3.6V

4.5

th(MO)

Master mode

1. Guaranteed by characterization results.

2. Excepting SPI1 with SCK IO=PA5. In this configuration, the maximum achievable frequency is 40 MHz.

3. Maximum frequency of the slave transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK

level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having

Tsu(MI)=0 while signal Duty(SCK)=50%.

Table 81. SPI dynamic characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MSv41658V1

NSS input

CPHA=0

CPOL=0

CPHA=0

CPOL=1

MISO output

MOSI input

tsu(SI)

th(SI)

tw(SCKL)

tw(SCKH)

tc(SCK)

tr(SCK)

th(NSS)

tdis(SO)

tsu(NSS)

ta(SO)

tv(SO)

Next bits IN

Last bit OUT

First bit IN

First bit OUT

Next bits OUT

th(SO)

tf(SCK)

Last bit IN

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