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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32F722IC 데이터시트(PDF) 194 Page - STMicroelectronics |
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STM32F722IC 데이터시트(HTML) 194 Page - STMicroelectronics |
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194 / 229 page  Electrical characteristics STM32F722xx STM32F723xx 194/229 DS11853 Rev 6 SDRAM waveforms and timings • CL = 30 pF on data and address lines. CL = 10 pF on FMC_SDCLK unless otherwise specified. In all timing tables, the THCLK is the HCLK clock period. – For 3.0 V ≤ VDD≤ 3.6 V, maximum FMC_SDCLK= 100 MHz at CL=20 pF (on FMC_SDCLK). – For 2.7 V ≤ VDD≤ 3.6 V, maximum FMC_SDCLK = 90 MHz at CL=30 pF (on FMC_SDCLK). – For 1.71 V ≤ VDD<1.9 V, maximum FMC_SDCLK = 70 MHz at CL=10 pF (on FMC_SDCLK). Figure 74. SDRAM read access waveforms (CL = 1) MS32751V2 Row n Col1 FMC_SDCLK FMC_A[12:0] FMC_SDNRAS FMC_SDNCAS FMC_SDNWE FMC_D[31:0] FMC_SDNE[1:0] td(SDCLKL_AddR) td(SDCLKL_AddC) th(SDCLKL_AddR) th(SDCLKL_AddC) td(SDCLKL_SNDE) tsu(SDCLKH_Data) th(SDCLKH_Data) Col2 Coli Coln Data2 Datai Datan Data1 th(SDCLKL_SNDE) td(SDCLKL_NRAS) td(SDCLKL_NCAS) th(SDCLKL_NCAS) th(SDCLKL_NRAS) |
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