ADSP-21486KSWZ-2AB datasheet(41/71 Pages) AD

41 / 71 page

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. H

Page 41 of 71

February 2020

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 38. IDP

signals are routed to the DAI_P20–1 pins using the SRU. There-

fore, the timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 38. Input Data Port (IDP)

Parameter

Min

Max

Unit

Timing Requirements

tSISFS

Frame Sync Setup Before Serial Clock Rising Edge

3.8

tSIHFS

Frame Sync Hold After Serial Clock Rising Edge

2.5

tSISD

Data Setup Before Serial Clock Rising Edge

2.5

tSIHD

Data Hold After Serial Clock Rising Edge

2.5

tIDPCLKW

Clock Width

(tPCLK × 4) ÷ 2 – 1

tIDPCLK

Clock Period

tPCLK × 4

1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG's input can

be either CLKIN or any of the DAI pins.

Figure 24. IDP Master Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tIDPCLK

tIDPCLKW

tSISFS

tSIHFS

tSIHD

tSISD

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