ADSP-21486KSWZ-2AB datasheet(48/71 Pages) AD

48 / 71 page

Rev. H

Page 48 of 71

February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

S/PDIF Receiver

The following section describes timing as it relates to the

S/PDIF receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 48. S/PDIF Receiver Internal Digital PLL Mode Timing

Parameter

Min

Max

Unit

Switching Characteristics

tDFSI

Frame Sync Delay After Serial Clock

tHOFSI

Frame Sync Hold After Serial Clock

–2

tDDTI

Transmit Data Delay After Serial Clock

tHDTI

Transmit Data Hold After Serial Clock

–2

tSCLKIW

Transmit Serial Clock Width

8 × tPCLK – 2

1 SCLK frequency is 64 × FS where FS = the frequency of frame sync.

Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

DRIVE EDGE

tSCLKIW

tDFSI

tHOFSI

tDDTI

tHDTI

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