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ADSP-21486KSWZ-2AB 데이터시트(PDF) 52 Page - Analog Devices

부품명 ADSP-21486KSWZ-2AB
상세설명  SHARC Processor
PDF  71 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADSP-21486KSWZ-2AB 데이터시트(HTML) 52 Page - Analog Devices

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Rev. H
|
Page 52 of 71
|
February 2020
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Figure 36. MLB Timing (3-Pin Interface)
Table 52. MLB Interface, 5-Pin Specifications
Parameter
Min
Typ
Max
Unit
5-Pin Characteristics
tMLBCLK
MLB Clock Period
512 FS
256 FS
40
81
ns
ns
tMCKL
MLBCLK Low Time
512 FS
256 FS
15
30
ns
ns
tMCKH
MLBCLK High Time
512 FS
256 FS
15
30
ns
ns
tMCKR
MLBCLK Rise Time (VIL to VIH)6
ns
tMCKF
MLBCLK Fall Time (VIH to VIL)6
ns
tMPWV
1
MLBCLK Pulse Width Variation
2
nspp
tDSMCF
2
DAT/SIG Input Setup Time
3
ns
tDHMCF
DAT/SIG Input Hold Time
5
ns
tMCDRV
DS/DO Output Data Delay From MLBCLK Rising Edge
8
ns
tMCRDL
3
DO/SO Low From MLBCLK High
512 FS
256 FS
10
20
ns
ns
CMLB
DS/DO Pin Load
40
pf
1 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp).
2 Gate Delays due to OR'ing logic on the pins must be accounted for.
3 When a node is not driving valid data onto the bus, the MLBSO and MLBDO output lines shall remain low. If the output lines can float at anytime, including while in reset,
external pull-down resistors are required to keep the outputs from corrupting the MediaLB signal lines when not being driven.
tMCKH
MLBSIG/
MLBDAT
(Rx, Input)
tMCKL
tMCKR
MLBSIG/
MLBDAT
(Tx, Output)
tMCFDZ
tDSMCF
MLBCLK
tMLBCLK
VALID
tDHMCF
tMCKF
tMCDRV
VALID
tMDZH



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