ADSP-21486KSWZ-2AB datasheet(54/71 Pages) AD

54 / 71 page

Rev. H

Page 54 of 71

February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

JTAG Test Access Port and Emulation

Table 53. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

tTCK

TCK Period

tSTAP

TDI, TMS Setup Before TCK High

tHTAP

TDI, TMS Hold After TCK High

tSSYS

1 System Inputs = DATA15–0, CLK_CFG1–0, RESET, BOOT_CFG2–0, DAI_Px, DPI_Px, and FLAG3–0.

System Inputs Setup Before TCK High

tHSYS

System Inputs Hold After TCK High

tTRSTW

TRST Pulse Width

4tCK

Switching Characteristics

tDTDO

TDO Delay from TCK Low

tDSYS

2 System Outputs = DAI_Px, DPI_Px ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK and EMU.

System Outputs Delay After TCK Low

tTCK ÷ 2 + 7

Figure 39. IEEE 1149.1 JTAG Test Access Port

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tTCK

tSTAP

tHTAP

tDTDO

tSSYS

tHSYS

tDSYS

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