LT8253EUFDM datasheet(10/20 Pages) AD

10 / 20 page

LT8253/LT8253A

Rev. 0

For more information www.analog.com

OPERATION

Main Control Loop

The LT8253/LT8253A are fixed frequency current mode

controllers. The inductor current is sensed through the

inductor sense resistor between the LSP and LSN pins.

The current sense voltage is gained up by amplifier A1

and added to a slope compensation ramp signal from the

internal oscillator. The summing signal is then fed into the

positive terminals of the buck current comparator A3 and

boost current comparator A4. The negative terminals of

A3 and A4 are controlled by the voltage on the VC pin,

which is the output of error amplifier EA1.

Depending on the state of the peak-buck peak-boost cur-

rent mode control, either the buck logic or the boost logic

is controlling the four power switches so that the FB volt-

age is regulated to 1V.

Light Load Current Operation

At light load, the LT8253/LT8253A typically run at discon-

tinuous conduction mode, to maintain the regulation and

improve the efficiency.

Shutdown and Power-On-Reset

The LT8253/LT8253A enter shutdown mode and drain

less than 2µA quiescent current when the EN/UVLO pin

is below its shutdown threshold (0.3V minimum). Once

the EN/UVLO pin is above its shutdown threshold (1V

maximum), the LT8253/LT8253A wake up startup cir-

cuitry, generate bandgap reference, and power up the

internal INTVCC LDO. The INTVCC LDO supplies the inter-

nal control circuitry and gate drivers. Then the LT8253/

LT8253A enter undervoltage lockout (UVLO) mode with

a hysteresis current (2.5µA typical) pulled into the EN/

UVLO pin. When the INTVCC pin is charged above its

rising UVLO threshold (3.78V typical), the EN/UVLO pin

passes its rising enable threshold (1.233V typical), and

the junction temperature is less than its thermal shutdown

(165°C typical), the LT8253/LT8253A enter enable mode,

in which the EN/UVLO hysteresis current is turned off

and the voltage reference VREF is being charged up from

ground. From the time of entering enable mode to the time

of VREF passing its rising UVLO threshold (1.89V typical),

the LT8253/LT8253A are going through a power-on-reset

(POR), waking up the entire internal control circuitry and

settling to the right initial conditions. After the POR, the

LT8253/LT8253A start switching.

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