LT8253EUFDM datasheet(15/20 Pages) AD

15 / 20 page

LT8253/LT8253A

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

CIN and COUT Selection

Input and output capacitance is necessary to suppress

voltage ripple caused by discontinuous current moving

in and out the regulator. A parallel combination of capaci-

tors is typically used to achieve high capacitance and low

equivalent series resistance (ESR). Dry tantalum, special

polymer, aluminum electrolytic and ceramic capacitors are

all available in surface mount packages. Capacitors with

low ESR and high ripple current ratings, such as OS-CON

and POSCAP are also available.

Ceramic capacitors should be placed near the regulator

input and output to suppress high frequency switching

spikes. Ceramic capacitors, of at least 1µF, should also

be placed from VIN to GND and VOUT to GND as close

to the LT8253/LT8253A pins as possible. Due to their

excellent low ESR characteristics, ceramic capacitors can

significantly reduce input ripple voltage and help reduce

power loss in the higher ESR bulk capacitors. X5R or X7R

dielectrics are preferred, as these materials retain their

capacitance over wide voltage and temperature ranges.

Many ceramic capacitors, particularly 0805 or 0603 case

sizes, have greatly reduced capacitance at the desired

operating voltage.

Input Capacitance CIN: Discontinuous input current is

highest in the buck region due to the switch A toggling

on and off. Make sure that the CIN capacitor network has

low enough ESR and is sized to handle the maximum RMS

current. In buck region, the input RMS current is given by:

IRMS � IOUT(MAX) •

VOUT

VIN

•

VIN

VOUT

� 1

The formula has a maximum at VIN = 2VOUT, where IRMS

= IOUT(MAX)/2. This simple worst-case condition is com-

monly used for design because even significant deviations

do not offer much relief.

Output Capacitance COUT: Discontinuous current shifts

from the input to the output in the boost region. Make sure

that the COUT capacitor network is capable of reducing the

output voltage ripple. The effects of ESR and the bulk

capacitance must be considered when choosing the right

capacitor for a given output ripple voltage. The maximum

steady state ripple due to charging and discharging the

bulk capacitance is given by:

� VCAP(BOOST) =

IOUT(MAX) • VOUT � VIN(MIN)

(

)

COUT • VOUT • f

� VCAP(BUCK) =

VOUT • 1�

VOUT

VIN(MAX)

�

��

�

÷÷

8 • L • f2 • COUT

The maximum steady ripple due to the voltage drop

across the ESR is given by:

� VESR(BOOST) =

VOUT •IOUT(MAX)

VIN(MIN)

• ESR

� VESR(BUCK) =

VOUT • 1�

VOUT

VIN(MAX)

�

��

�

÷÷

L • f

• ESR

INTVCC Regulator

An internal P-channel low dropout regulator produces

5V at the INTVCC pin from the VIN supply pin. The INTVCC

powers internal circuitry and gate drivers in the LT8253/

LT8253A. The INTVCC regulator must be bypassed to

ground with a minimum of 4.7µF ceramic capacitor. Good

local bypass is necessary to supply the high transient

current required by MOSFET gate drivers.

Higher input voltage applications with large MOSFETs

being driven at higher switching frequencies may cause

the maximum junction temperature rating for the LT8253/

LT8253A to be exceeded. The system supply current is

normally dominated by the gate charge current. Additional

external loading of the INTVCC also needs to be taken into

account for the power dissipation calculation. The total

LT8253/LT8253A power dissipation in this case is VIN •

IINTVCC, and overall efficiency is lowered. The junction

temperature can be estimated by using the equation:

TJ = TA + PD •

θJA

where

θJA (in °C/W) is the package thermal resistance.

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