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WM8569

w

PP Rev 1.1 December 2005

17

AUDIO INTERFACE FORMATS

Audio data is applied to the internal DAC filters or output from the ADC filters, via the Digital Audio

Interface. 5 popular interface formats are supported:

•

Left Justified mode

•

Right Justified mode

•

I

•

DSP Mode A

•

DSP Mode B

All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the

exception of 32 bit right justified mode, which is not supported.

In left justified, right justified and I

input and outputs ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with

DACLRC/ADCLRC indicating whether the left or right channel is present. DACLRC/ADCLRC is also

used as a timing reference to indicate the beginning or end of the data words.

In left justified, right justified and I

times the selected word length. LRC must be high for a minimum of word length BCLKs and low for a

minimum of word length BCLKs. Any mark to space ratio on LRC is acceptable provided the above

requirements are met.

In DSP mode A or B, the DAC channels are time multiplexed onto DIN. LRC is used as a frame sync

signal to identify the MSB of the first word. The minimum number of DACBCLKs per DACLRC period

is 6 times the selected word length. Any mark to space ratio is acceptable on DACLRC provided the

rising edge is correctly positioned. The ADC data may also be output in DSP mode A or B, with

ADCLRC used as a frame sync to identify the MSB of the first word. The minimum number of

ADCBCLKs per ADCLRC period is 2 times the selected word length if only the ADC is being

operated.

LEFT JUSTIFIED MODE

In left justified mode, the MSB of DIN is sampled by the WM8569 on the first rising edge of

DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and

changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the rising edge

of BCLK. LRC is high during the left samples and low during the right samples (Figure 11).

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN1/2/3/

DOUT

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

Figure 11 Left Justified Mode Timing Diagram

RIGHT JUSTIFIED MODE

In right justified mode, the LSB of DIN is sampled by the WM8569 on the rising edge of DACBCLK

preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the

falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of

ADCBCLK. LRC are high during the left samples and low during the right samples (Figure 12).