WM8569

Product Preview

w

PP Rev 1.1 December 2005

18

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN1/2/3/

DOUT

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

Figure 12 Right Justified Mode Timing Diagram

I

In I

following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the

first falling edge of ADCBCLK following an ADCLRC transition and may be sampled on the rising

edge of ADCBCLK. LRC are low during the left samples and high during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN1/2/3/

DOUT

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

1 BCLK

1 BCLK

Figure 13 I

DSP MODE A

In DSP mode A, the MSB of DAC left channel data is sampled by the WM8569 on the second rising

edge on DACBCLK following a DACLRC rising edge. DAC right channel follows DAC left channel

(Figure 14).

Figure 14 DSP Mode A Timing Diagram – DAC Data Input

The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of

ADCBCLK following a low to high ADCLRC transition and may be sampled on the rising edge of

ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 15)