ADRF5132

Data Sheet

Rev. B | Page 8 of 12

THEORY OF OPERATION

The ADRF5132 requires a single-supply voltage applied to the

to minimize RF coupling.

The ADRF5132 is controlled via a digital control voltage

isolation.

The ADRF5132 is internally matched to 50 Ω at the RF input

port (RFC) and the RF output ports (RF1 and RF2); therefore,

no external matching components are required. The RFx (RFC,

RF1, and RF2) pins are dc-coupled, and dc blocking capacitors

are required on the RFx lines. The design is bidirectional; the

input and outputs are interchangeable.

The ideal power-up sequence is as follows:

1. Connect the device to ground.

3. Power up the digital control input. Powering the digital

forward bias and damage ESD protection structures.

4. Power up the RF input. Depending on the logic level

RF1) is set to on mode, by which an insertion loss path is

provided from RFC to the output, while the other RF

output port (for example, RF2) is set to off mode, by which

the output is isolated from RFC.

Table 6. Switch Operation Mode

Digital Control Input,

Switch Mode

RFC to RF1

RFC to RF2

1

Off mode: the RF1 port is isolated from RFC and is

reflective.

On mode: a low insertion loss path from RFC to the RF2

port.

0

On mode: a low insertion loss path from RFC to the RF1

port.

Off mode: the RF2 port is isolated from RFC and is

reflective.